Introduction

A serial NOR Flash device delivers its full performance only when the read timing and the board layout are designed with care. The device itself supports the fast read and the execute-in-place, but the dummy cycles, the trace length and the decoupling decide whether the read is reliable across the temperature range. This application note explains the practical rules for applying a GigaDevice GD25 SPI NOR Flash on an embedded board.

Execute-in-Place

Execute-in-place means the processor fetches and runs the code directly from the flash without copying it to RAM first. It saves the RAM and the boot time, and it is the reason serial NOR is the default boot device. For the in-place execution to work, the read must keep up with the core, so the flash is used in the fast-read mode and, where the pin budget allows, in the Quad SPI mode, and the processor cache and prefetch are set to hide the latency.

Cache and Prefetch

A cache or a prefetch buffer on the processor hides the flash latency for a sequential code fetch, so set it as the processor datasheet recommends and confirm the effect on the loop timing. Where the code is executed from the flash, the cache miss rate is what sets the worst-case performance.

Read Timing and Dummy Cycles

The fast-read and the Quad-I/O read commands need a number of dummy cycles between the address and the data, and the number depends on the clock. Set the dummy cycles as the datasheet specifies for the chosen clock, and confirm the read waveform on the bench, because a wrong dummy-cycle setting is a common cause of an intermittent boot failure that appears only at a certain temperature or clock. Measure the read at the worst-case clock and temperature and check the setup and the hold margins.

The Clock and the Mode

Choose the read mode and the clock from the throughput the core needs, and remember that a higher clock leaves less margin for the trace length. Where the board is large or the environment is noisy, a slightly lower clock with a good layout is more reliable than the maximum clock with a marginal one.

Layout and Signal Integrity

Keep the SPI traces short and matched, place the decoupling capacitor close to the supply pins and keep the clock trace away from the switching nodes. Use a ground plane and keep the loop small, and add a small series resistor on the clock where the edge is fast and the trace is long. The goal is a clean clock and data eye at the flash pins across the temperature range.

Decoupling and Power

The write and the erase draw current in bursts, so the supply must be stable: place the recommended decoupling capacitor close to the supply pins and keep the supply trace short. A weak supply during a write is a common cause of a corrupt sector, so a clean supply also protects the data.

Write Protection and Security

The device offers software and hardware write protection, top and bottom block protection, security registers with one-time-programmable locks and a 128-bit unique ID. Use them to protect the boot code from an accidental write and to store an identity or a key for a secure-boot scheme. Plan the protection region and the unlock sequence before the firmware is written, because changing them later is difficult.

Validation

Validate on the bench by reading and erasing across the temperature range, by confirming the boot under the worst-case conditions and by checking the read eye with a scope. Measure the current during a write and confirm the supply is stable, and run a long erase and program cycle test to confirm the endurance. Our FAE team can review your timing and layout and help you interpret the measurements, so the flash performs in the product as it does on the datasheet.